Integrated circuits (ICs) have traditionally implemented a single function, or plural functions, defined by software programming. In such integrated circuits, the logic architecture that implemented the functionality was fixed during the design of the IC. Recently, integrated circuits have been developed where the logic function can be changed after manufacture. For example, FPGAs have been developed with logic functions that can be configured by the user. They are comprised, at least in part, of a matrix of programmable logic cells. Each programmable logic cell includes routing conductors to receive input signals from outside the cell and to conduct signals to the periphery of the cell for interconnection to other cells. The routing conductors include programmable interconnects for selectively interconnecting routing conductors in the same cell, or for selectively interconnecting routing conductors from one cell to routing conductors of another cell.
In addition to the routing conductors and programmable interconnects, each cell includes a PFU. A PFU is also known as a configurable logic block (CLB) or configurable logic element (CLE) as, for example, in U.S. Pat. No. 4,870,302. A PFU is a repetitive subunit within a FPGA. The PFU receives inputs such as logic level signals and a clock signal on interconnecting routing conductors, operates on the input signals in a predetermined manner dependent on how the PFU is user-configured, and provides selected output signals. The PFU output signals are provided by output drivers.
Each PFU may include more than one type of circuitry capable of logic functions. Typical circuitry included in PFUs includes combinatorial logic circuits and sequential logic circuits. The combinatorial logic circuits generally provide the basic building blocks for combinatorial logic such as AND and OR functions. The sequential logic circuit functions are generally provided by registers. The registers can be configured as flip-flops or latches.
Each PFU typically includes circuitry to perform both types of logic functions, sequential and combinatorial, with a fixed number of each type. The output from the sequential or combinatorial logic circuits has typically been provided to the routing conductors, sometimes referred to as a resistor-capacitor routing resource tree, through PFU output drivers. Each driver has been coupled to the output of one or a subset of the sequential or combinatorial logic circuits.
Some prior an FPGAs have coupled each sequential or combinatorial logic circuit output to a dedicated PFU output driver. With dedicated PFU output drivers, a large number of output drivers have been provided to assure that each logic circuit output was available as an output of the PFU. However, not all logic circuit outputs are used in all PFUs. Since each output driver increases the physical area required to manufacture a FPGA, this is not an efficient technique to provide PFU outputs. Furthermore, the PFU driver output in a dedicated PFU application cannot be used to provide sequential or combinatorial logic circuit outputs other than the logic circuit output to which the driver is dedicated.
Other prior an FPGAs have provided a plurality of multiplexers each coupled between the output of a subset of the PFU sequential or combinatorial logic circuits and a PFU output driver. The multiplexer is user configured to select one of the sequential or combinatorial logic circuit outputs to couple to the PFU driver. The selected sequential or combinatorial logic circuit output is provided as an output of the PFU. This technique has the shortcoming that only one of the sequential or combinatorial logic function circuit outputs of the subset is available as an output from the PFU at any one time. Also, since a multiplexer serves a subset of the PFU sequential or combinatorial logic circuits, multiple PFU drivers cannot be coupled to the same sequential or combinatorial logic circuit to provide multiple, identical outputs from the PFU.
Both of the above-mentioned prior an FPGAs have the further shortcoming that the output from a sequential or combinatorial logic circuit is predetermined to be a specific one of the outputs from the PFU. This has two adverse consequences. Firstly, each PFU output driver generally has different connectivity to the FPGA routing resources. Therefore, it may be less efficient to route a particular sequential or combinatorial logic circuit output signal to its destination outside the originating PFU from one output driver rather than from another output driver. Secondly, since each sequential or combinatorial logic circuit output signal can be driven onto only one PFU output driver, the output driver must source current to drive the entire resistor-capacitor routing resource tree for that output signal. This latter shortcoming was addressed in prior art FPGAs by placing a buffer outside the PFU, in series with the output driver within the PFU, to isolate and drive pan of the resistor-capacitor routing resource tree. However, the buffer would introduce a delay in the PFU output signal that would degrade the FPGA performance.
What is desirable is a FPGA having a versatile PFU including PFU drivers with inputs that can be selectively or programmably coupled to the sequential or combinatorial logic circuit outputs. Such a PFU would provide for efficient connectivity to the FPGA routing resources. Such a PFU would also achieve greater flexibility in structuring the resistor-capacitor routing resource tree without degrading the speed of the FPGA when the output of a sequential or combinatorial logic circuit is expanded. Furthermore, such a FPGA would permit the user during configuration of the FPGA to select the outputs of the PFU from all of the sequential or combinatorial logic function circuit outputs. The outputs of the PFU could be provided utilizing fewer output drivers than sequential or combinatorial logic circuits.